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august 200 4 asmp5p2304a rev 2.0 alliance semiconductor 2575, augustine drive ? santa clara, ca ? tel: 408.855.4900 ? fax: 408.855.4999 ? www.alsc.com notice: the information in this document is subject to change withou t notice. 3.3 v zero delay buffer features ? zero input - output propagation delay, adjustable by capacitive load on fbk input. ? multiple configurations - refer ? input frequency range: 10mhz to 133mhz ? multiple low - skew outputs. ? out put - output skew less than 200 ps. ? device - device skew less than 500 ps. ? two banks of four outputs. ? less than 200 ps cycle - to - cycle jitter ( - 1, - 1h, - 5h). ? available in space saving, 8 - pin 150 - mil soic packages and standard tssop . ? 3.3v operation. ? advanced 0.3 5 cmos technology. ? industrial temperature available. functional description asm5p2304a is a versatile, 3.3v zero - delay buffer designed to distribute high - speed clocks in pc, workstation , datacom, telecom and other high - performance applications. it is a vailable in a 8 - pin package. the part has an on - chip pll which locks to an input clock presented on the ref pin. the pll feedback is required to be driven to fbk pin, and can be obtained from one of the outputs. the input - to - output propagation delay is gua ranteed to be less than 250ps, and the output - to - output skew is guaranteed to be less than 200ps. the asm5p2304a has two banks of two outputs each. multiple asm5p2304a devices can accept the same input clock and distribute it. in this case the skew betwee n the outputs of the two devices is guaranteed to be less than 500ps. the asm5p2304a is available in two different block diagram fbk ref pll /2 clka 1 clka2 clkb1 clkb2 extra divider ( - 2)
august 200 4 asm5p2304a rev 2.0 3.3 zero delay buffer 2 of 13 notice: the information in this document is subject to change without notice. asm5p2304a configuration s device feedback f rom bank a frequency bank b frequency asm5p2304a - 1 bank a or bank b reference reference asm5p2304a - 1h bank a or bank b reference reference asm5p2304a - 2 bank a reference reference /2 asm5p2304a - 2 bank b 2 x reference reference asm5p2304a - 5h bank a or bank b reference /2 reference /2 zero delay and skew control for applications requiring zero input - output delay, all outputs must be equally loaded. to close the feedback loop of the asm5p2304a, the fbk pin can be driven fr om any of the four available output pins. the output driving the fbk pin will be driving a total load of 7 pf plus any additional load that it drives. the relative loading of this output (with respect to the remaining outputs) can adjust the input output d elay. this is shown in the above graph. for applications requiring zero input - output delay, all outputs including the one providing feedback should be equally loaded. if input - output delay adjustments are required, use the above graph to calculate loading differences between the feedback output and remaining outputs. for zero output - output skew, be sure to load outputs equally. - 30 - 25 - 20 - 15 - 10 - 5 0 5 10 15 20 25 30 0 - 500 - 1000 - 1500 500 1000 1500 output load difference: fbk load - clka/clkb load (pf) r e f - i n p u t t o c l k a / c l k b d e l a y ( p s ) ref input to clka/clkb delay vs difference in loading between fbk pin and clka/clkb pins
august 200 4 asm5p2304a rev 2.0 3.3 zero delay buffer 3 of 13 notice: the information in this document is subject to change without notice. pin configuration pin description for asm5p2304a pin # pin name description 1 ref 1 input ref erence frequency, 5v tolerant input 2 clka1 2 buffered clock output, bank a 3 clka2 2 buffered clock output, bank a 4 gnd ground 5 clkb1 2 buffered clock output, bank b 6 clkb2 2 buffered clock output, bank b 7 v dd 3.3v supply 8 fbk pll feedback input notes: 1. weak pull - down. 2. weak pull - down on all outputs. 1 2 3 4 ref clka1 clka2 clkb1 clkb2 v dd gnd fbk asm5p2304a 8 7 6 5
august 200 4 asm5p2304a rev 2.0 3.3 zero delay buffer 4 of 13 notice: the information in this document is subject to change without notice. absolute maximum ratings parameter min max unit supply voltage to ground potential - 0.5 +7.0 v dc input voltage (except ref) - 0.5 v dd + 0.5 v dc input voltage (ref) - 0.5 7 v storage tem perature - 65 +150 ?c max. soldering temperature (10 sec) 260 ?c junction temperature 150 ?c static discharge voltage (per mil - std - 883, method 3015) >2000 v note: these are stress ratings only and functional usage is not implied. exposure to absolute maximum ratings for prolonged periods can affect device reliability. operating conditions for asm5p2304a commercial temperature devices parameter description min max unit v dd supply voltage 3.0 3.6 v t a operating temperature (ambient temperature ) 0 70 ?c c l load capacitance, below 100 mhz 30 pf c l load capacitance, from 100 mhz to 133 mhz 15 pf c in input capacitance 3 7 pf note: 3. applies to both ref clock and fbk.
august 200 4 asm5p2304a rev 2.0 3.3 zero delay buffer 5 of 13 notice: the information in this document is subject to change without notice. electrical characteristics for asm5p2304a commercial temperature device s parameter description test conditions min max unit v il input low voltage 0.8 v v ih input high voltage 2.0 v i il input low current v in = 0v 50.0 a i ih input high current v in = v dd 100.0 a v ol output low voltage 4 i ol = 8ma ( - 1, - 2) i oh = 1 2ma ( - 1h, - 5h) 0.4 v v oh output high voltage 4 i ol = - 8ma ( - 1, - 2) i oh = - 12ma ( - 1h, - 5h) 2.4 v tbd unloaded outputs 100mhz ref, select inputs at v dd or gnd tbd unloaded outputs, 66mhz ref ( - 1, - 2) tbd i dd supply current unloaded out puts, 33mhz ref ( - 1, - 2) tbd ma note: 4. parameter is guaranteed by design and characterization. not 100% tested in production.
august 200 4 asm5p2304a rev 2.0 3.3 zero delay buffer 6 of 13 notice: the information in this document is subject to change without notice. switching characteristics for asm5p2304a commercial temperature devices paramete r description test conditions min typ max u nit t 1 output frequency 30 - pf load, all devices 10 100 mhz t 1 output frequency 20 - pf load, - 1h, - 5h devices 10 133.3 mhz t 1 output frequency 15 - pf load, - 1, - 2 devices 10 133.3 mhz duty cycle 4 = (t 2 / t 1 ) * 100 ( - 1, - 2, - 1h, - 5h) measured at 1.4v, f out = 66.66 mhz 30 - pf load 40.0 50.0 60.0 % duty cycle 4 = (t 2 / t 1 ) * 100 ( - 1, - 2, - 1h, - 5h) measured at 1.4v, f out = <50 mhz 15 - pf load 45.0 50.0 55.0 % t 3 output rise time 4 ( - 1, - 2) measured between 0.8v and 2.0v 30 - pf load 2.20 ns t 3 output ris e time 4 ( - 1, - 2) measured between 0.8v and 2.0v 15 - pf load 1.50 ns t 3 output rise time 4 ( - 1h, - 5h) measured between 0.8v and 2.0v 30 - pf load 1.50 ns t 4 output fall time 4 ( - 1, - 2) measured between 2.0v and 0.8v 30 - pf load 2.20 ns t 4 output fall time 4 ( - 1, - 2) measured between 2.0v and 0.8v 15 - pf load 1.50 ns t 4 output fall time 4 ( - 1h, - 5h) measured between 2.0v and 0.8v 30 - pf load 1.25 ns output - to - output skew on same bank ( - 1, - 2) 4 all outputs equally loaded 200 output - to - outp ut skew ( - 1h, - 5h) all outputs equally loaded 200 output bank a - to - output bank b skew ( - 1, - 5h) all outputs equally loaded 200 t 5 output bank a to output bank b skew ( - 2) all outputs equally loaded 400 ps t 6 delay, ref rising edge to fbk rising edge 3 measured at v dd /2 0 250 ps t 7 device - to - device skew 4 measured at v dd /2 on the fbk pins of the device 0 500 ps t 8 output slew rate 4 measured between 0.8v and 2.0v using test circuit #2 1 v/ns meas ured at 66.67 mhz, loaded outputs, 15 pf load 175 measured at 66.67 mhz, loaded outputs, 30 pf load 200 t j cycle - to - cycle jitter 4 ( - 1, - 1h, - 5h) measured at 133.3 mhz, loaded outputs, 15 pf load 100 ps measured at 66.67 mhz, loaded outputs, 30pf lo ad 400 t j cycle - to - cycle jitter 4 ( - 2,) measured at 66.67 mhz, loaded outputs, 15 pf load 375 ps t lock pll lock time 4 stable power supply, valid clock presented on ref and fbk pins 1.0 ms
august 200 4 asm5p2304a rev 2.0 3.3 zero delay buffer 7 of 13 notice: the information in this document is subject to change without notice. operating conditions for asm5i2304a industrial temperature devices parameter descripti on min max unit v dd supply voltage 3.0 3.6 v t a operating temperature (ambient temperature) - 40 85 ?c c l load capacitance, below 100 mhz 30 pf c l load capacitance, from 100 mhz to 133 mhz 15 pf c in input capacitance 3 7 pf electrical characteristi cs for asm5i2304a industrial temperature devices parameter description test conditions min max unit v il input low voltage 0.8 v v ih input high voltage 2.0 v i il input low current v in = 0v 50.0 a i ih input high current v in = v dd 100.0 a v ol output low voltage 4 i ol = 8ma ( - 1, - 2) i oh = 12ma ( - 1h, - 5h) 0.4 v v oh output high voltage 4 i ol = - 8ma ( - 1, - 2) i oh = - 12ma ( - 1h, - 5h) 2.4 v tbd unloaded outputs 100mhz ref, select inputs at v dd or gnd tbd unloaded out puts, 66mhz ref ( - 1, - 2) tbd i dd supply current unloaded outputs, 33mhz ref ( - 1, - 2) tbd ma
august 200 4 asm5p2304a rev 2.0 3.3 zero delay buffer 8 of 13 notice: the information in this document is subject to change without notice. switching characteristics for asm5i2304a industrial temperature devices all parameters are specified with loaded outputs parameter description test conditions min typ max un it t 1 output frequency 30 - pf load, all devices 10 100 mhz t 1 output frequency 20 - pf load, - 1h, - 5h devices 10 133.3 mhz t 1 output frequency 15 - pf load, - 1 and - 2 devices 10 133.3 mhz duty cycle 4 = (t 2 / t 1 ) * 100 ( - 1, - 2, - 1h, - 5h) measured at 1. 4v, f out = <66.66 mhz 30 - pf load 40.0 50.0 60.0 % duty cycle 4 = (t 2 / t 1 ) * 100 ( - 1, - 2, - 1h, - 5h) measured at 1.4v, f out = <50 mhz 15 - pf load 45.0 50.0 55.0 % t 3 output rise time 4 ( - 1, - 2) measured between 0.8v and 2.0v 30 - pf load 2.50 ns t 3 output rise time 4 ( - 1, - 2) measured between 0.8v and 2.0v 15 - pf load 1.50 ns t 3 output rise time 4 ( - 1h, - 5h) measured between 0.8v and 2.0v 30 - pf load 1.50 ns t 4 output fall time 4 ( - 1, - 2) measured between 2.0v and 0.8v 30 - pf load 2.50 ns t 4 output f all time 4 ( - 1, - 2) measured between 2.0v and 0.8v 15 - pf load 1.50 ns t 4 output fall time 4 ( - 1h, - 5h) measured between 2.0v and 0.8v 30 - pf load 1.25 ns output - to - output skew on same bank ( - 1, - 2) 4 all outputs equally loaded 200 output - to - output skew ( - 1h, - 5h) all outputs equally loaded 200 output bank a - to - output bank b skew ( - 1, - 5h) all outputs equally loaded 200 t 5 output bank a - to - output bank b skew ( - 2) all outputs equally loaded 400 ps t 6 delay, ref rising edge to fbk rising edge 4 measured at v dd /2 0 250 ps t 7 device - to - device skew 4 measured at v dd /2 on the fbk pins of the device 0 500 ps t 8 output slew rate 4 measured between 0.8v and 2.0v using test circuit #2 1 v/ns measured at 66.67 mhz, loaded outputs, 15 pf load 180 measured at 66.67 mhz, loaded outputs, 30 pf load 200 t j cycle - to - cycle jitter 4 ( - 1, - 1h, - 5 h) measured at 133.3 mhz, loaded outputs, 15 pf load 100 ps measured at 66.67 mhz, loaded outputs, 3 0pf load 400 t j cycle - to - cycle jitter 4 ( - 2) measured at 66.67 mhz, loaded outputs, 15 pf load 380 ps t lock pll lock time 4 stable power supply, valid clock presented on ref and fbk pins 1.0 ms
august 200 4 asm5p2304a rev 2.0 3.3 zero delay buffer 9 of 13 notice: the information in this document is subject to change without notice. switching waveforms duty cycle timing all outpu ts rise/fall time output - output skew input - output propagation delay device - device skew t 1 t 2 1.4 v 1.4 v 1.4 v output 2.0 v 0.8 v t3 t4 3.3 v 0 v 2.0 v 0.8 v 1.4 v 1.4 v t 5 output output v dd /2 t 6 input output v dd /2 v dd /2 t 7 fbk, device 1 v dd /2 fbk, device 2
august 200 4 asm5p2304a rev 2.0 3.3 zero delay buffer 10 of 13 notice: the information in this document is subject to change without notice. test circuits 1k ? 10 pf v dd gnd outputs c load 0.1 ?f 1k ? 0.1 ?f 0.1 ?f 0.1 ?f v dd v dd v dd gnd gnd gnd outputs test circuit #1 test circuit #2 for parameter t 8 (output slew rate) on - 1h devices
august 200 4 asm5p2304a rev 2.0 3.3 zero delay buffer 11 of 13 notice: the information in this document is subject to change without notice. package information: 8 - lead (150 mil) molded soic dimensions in inches dimensions in millimeters symbo l min max min max a 0.053 0.069 1.35 1.75 a1 0.004 0.010 0.10 0.25 b 0.013 0.022 0.33 0.53 c 0.007 0.012 0.18 0.27 d 0.188 0.197 4.78 5.00 e 0.150 0.158 3.80 4.01 h 0.228 0.244 5.80 6.20 e 0.050 bsc 1.27 bsc l 0.016 0.035 0.40 0.89 ? d e h d a1 a ? l c b e
august 200 4 asm5p2304a rev 2.0 3.3 zero delay buffer 12 of 13 notice: the information in this document is subject to change without notice. ordering code package type operating range asm5p2304a - 1 - 08 - sr 8 - pin 150 - mil soic - tape & reel commercial asm5p2304a - 1 - 08 - st 8 - pin 150 - mil soic - tube commercial asm5i2304a - 1 - 08 - sr 8 - pin 150 - mil soic - tape & reel industrial asm5i2304a - 1 - 08 - st 8 - pin 150 - mil soic - tube industrial asm5p2304a - 1h - 08 - sr 8 - pin 150 - mil soic - tape & reel commercial asm5p2304a - 1h - 08 - st 8 - pin 150 - mil soic - tube commercial asm5i2304a - 1h - 08 - sr 8 - pin 150 - mil soic - tape & reel industrial asm5i2304a - 1h - 08 - st 8 - pin 150 - mil soic - tube industrial asm5p2304a - 2 - 08 - sr 8 - pin 150 - mil soic - tape & reel commercial asm5p2304a - 2 - 08 - st 8 - pin 150 - mil soic - tube commercial asm5i2304a - 2 - 08 - sr 8 - pin 150 - mil soic - tape & reel industrial asm5i2304a - 2 - 08 - st 8 - pin 150 - mil soic - tube industrial asm5p2304a - 5h - 08 - sr 8 - pin 150 - mil soic - tape & reel commercial asm5p2304a - 5h - 08 - st 8 - pin 150 - mil soic - tube commercial asm5i2304a - 5h - 08 - sr 8 - pin 150 - mil soic - tape & reel industrial asm5i2304a - 5h - 08 - st 8 - pin 150 - mil soic - tube industrial licensed und er us patent nos 5,488,627 , 6,646,463 and 5,631,920. preliminary datasheet. specification subject to change without notice.
august 200 4 asm5p2304a rev 2.0 3.3 zero delay buffer 13 of 13 notice: the information in this document is subject to change without notice. device ordering information package suffix asm5p2304a f - 08-or * * * note: industry standard part numbers may be used that differ from this part numbering system... alliance semiconductor mixed signal product x= automotive i= industrial p or n/c = commercial 1 = reserved 6 = power management * * * 2 = non pll based 7 = power management * * * 3 = emi reduction 8 = power management * * * 4 = ddr support products 9 = hi performance 5 = std zero delay buffer 0 = reserved part number or = sot23/ t/r sr = soic,t/r tt = tssop, tube jt = ssop, tube tr = tssop, t/r jr = ssop, t/r vt = tvsop,tube qr = qfn, t/r vr = tvsop, t/r qt = qfn, tube st = soic, tube bt = bga, tube br = bga, t/r f = pb free device pin count ? copyright 2003 alliance semiconductor corporation. all rights reserved. our three - po int logo, our name and intelliwatt are trademarks or registered trademarks of alliance. all other brand and product names may be the trademarks of their respective companies. alliance reserves the right to make changes to this document and its products at any time without notice. alliance assumes no responsibility for any errors that may appear in this document. the data contained herein represents alliance's best data and/or estimates at the time of issuance. alliance reserves the right to change or correc t this data at any time, without notice. if the product described herein is under development, significant changes to these specifications are possible. the information in this product data sheet is intended to be general descriptive information for potent ial customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as e xpress agreed to in alliance's terms and conditions of sale (which are available from alliance). all sales of alliance products are made exclusively according to alliance's terms and conditions of sale. the purchase of products from alliance does not conve y a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of alliance or third parties. alliance does not authorize its products for use as critical components in life - supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of alliance products in such life - supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify alli ance against all claims arising from such use. alliance semiconductor corporation 2595, augustine drive, santa clara, ca 95054 tel# 408 - 855 - 4900 fax: 408 - 855 - 4999 www.alsc.com copyright ? alliance semiconductor all rights reserved note: this product utilizes us# 6,646,463 impedance emulator patent issued to dan hariton / alliance semiconductor, dated 11 - 11 - 2003 part number: asm5p2304 a document version: 2.0 8_30 _2004 use the chart below for device ordering *

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